The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e. the number of interconnected devices per chip area) has generally increased while geometry size (i.e. the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease.
However, the scaling of CMOS devices faces challenges of rapid increase in power consumption. Impact-ionization MOS (IMOS) devices are a promising candidate for enabling further scaling of power supply voltage without an increase of an off-state leakage current due to its sub-60 mV/dec subthreshold swing. Therefore, what is desired is a method of fabricating a IMOS device utilizing high-k dielectric metal gate technology.